may 2009 FDMS6681Z p-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation FDMS6681Z rev.c4 www.fairchildsemi.com 1 FDMS6681Z p-channel powertrench ? mosfet -30 v, -49 a, 3.2 m : features ? max r ds(on) = 3.2 m : at v gs = -10 v, i d = -21.1 a ? max r ds(on) = 5.0 m : at v gs = -4.5 v, i d = -15.7 a ? advanced package and silicon combination for low r ds(on) ? hbm esd protection level of 8kv typical(note 3) ? msl1 robust package design ? rohs compliant general description the FDMS6681Z has been designed to minimize losses in load switch applications. advancements in both silicon and package technologies have been combined to offer the lowest r ds(on) and esd protection. applications ? load switch in notebook and server ? notebook battery pack power management g s s s d d d d 5 6 7 8 3 2 1 4 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking a nd ordering information symbol parameter ratings units v ds drain to source voltage -30 v v gs gate to source voltage 25 v i d drain current -continuous (package limited) t c = 25 c -49 a -continuous (silicon limited) t c = 25 c -116 -continuous t a = 25 c (note 1a) -21.1 -pulsed -90 p d power dissipation t c = 25 c 73 w power dissipation t a = 25 c (note 1a) 2.5 t j , t stg operating and storage junction temperature range -55 to +150 c r t jc thermal resistance, junction to case 1.7 c/w r t ja thermal resistance, junction to ambient (note 1a) 50 device marking device package reel size tape width quantity FDMS6681Z FDMS6681Z power 56 13 ?? 12 mm 3000 units bottom power 56 top pin 1 g s s s d d d d www.datasheet.co.kr datasheet pdf - http://www..net/
FDMS6681Z p-channel powertrench ? mosfet www.fairchildsemi.com 2 ?2009 fairchild semiconductor corporation FDMS6681Z rev.c4 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics notes: 1. r t ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r t jc is guaranteed by design while r t ca is determined by the user's board design. 2. pulse test: pulse width < 300 p s, duty cycle < 2.0%. 3. the diode connected between the gate and source servers on ly as protection against esd. no gate overvoltage rating is impli ed. symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 p a, v gs = 0 v -30 v ' bv dss ' t j breakdown voltage temperature coefficient i d = -250 p a, referenced to 25 c 20 mv/c i dss zero gate voltage drain current v ds = -24 v, v gs = 0 v -1 p a i gss gate to source leakage current v gs = 25 v, v ds = 0 v 10 p a v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 p a-1-1.7-3v ' v gs(th) ' t j gate to source threshold voltage temperature coefficient i d = -250 p a, referenced to 25 c -7 mv/c r ds(on) static drain to source on resistance v gs = -10 v, i d = -22.1 a 2.7 3.2 m : v gs = -4.5 v, i d = -15.7 a 4.0 5.0 v gs = -10 v, i d = -22.1 a, t j = 125 c 3.9 5.0 g fs forward transconductance v dd = -10 v, i d = -22.1 a 143 s c iss input capacitance v ds = -15 v, v gs = 0 v, f = 1 mhz 7803 10380 pf c oss output capacitance 1540 2050 pf c rss reverse transfer capacitance 1345 2020 pf t d(on) turn-on delay time v dd = -15 v, i d = -22.1 a, v gs = -10 v, r gen = 6 : 15 24 ns t r rise time 38 61 ns t d(off) turn-off delay time 260 416 ns t f fall time 197 316 ns q g total gate charge v gs = 0 v to -10 v v dd = -15 v, i d = -22.1 a 172 241 nc q g total gate charge v gs = 0 v to -5 v 97 136 nc q gs gate to source charge 22 nc q gd gate to drain ?miller? charge 46 nc v sd source to drain diode forward voltage v gs = 0 v, i s = -2.1 a (note 2) 0.68 1.2 v v gs = 0 v, i s = -22.1 a (note 2) 0.79 1.25 v t rr reverse recovery time i f = -22.1 a, di/dt = 100 a/ p s 44 71 ns q rr reverse recovery charge 39 63 nc b. 125 c/w when mounted on a minimum pad of 2 oz copper. a. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper. www.datasheet.co.kr datasheet pdf - http://www..net/
FDMS6681Z p-channel powertrench ? mosfet www.fairchildsemi.com 3 ?2009 fairchild semiconductor corporation FDMS6681Z rev.c 4 typical characteristics t j = 25 c unless otherwise noted figure 1. 0123 0 15 30 45 60 75 90 v gs = -3 v v gs = -3.5 v -v ds , drain to source voltage (v) -i d , drain current (a) pulse duration = 80 p s duty cycle = 0.5% max v gs = -4 v v gs = -10v v gs = -4.5 v on region characteristics figure 2. 0 153045607590 0 1 2 3 4 5 v gs = -4.5 v v gs = -3.5 v pulse duration = 80 p s duty cycle = 0.5%max normalized drain to source on-resistance -i d , drain current (a) v gs = -4 v v gs = -3 v v gs =-10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = -22.1 a v gs = -10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 246810 0 3 6 9 12 t j = 125 o c i d = -22.1 a t j = 25 o c -v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 01234 0 15 30 45 60 75 90 -v gs , gate to source voltage (v) -i d , drain current (a) t j = 150 o c v ds = -5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c figure 6. 0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current www.datasheet.co.kr datasheet pdf - http://www..net/
FDMS6681Z p-channel powertrench ? mosfet www.fairchildsemi.com 4 ?2009 fairchild semiconductor corporation FDMS6681Z rev.c 4 figure 7. 0 50 100 150 200 0 2 4 6 8 10 q g , gate charge (nc) -v gs , gate to source voltage (v) i d = -22.1 a v dd = -15 v v dd = -20 v v dd = -10 v gate charge characteristics figure 8. 0.1 1 10 600 1000 10000 20000 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss 30 c a p a c i t a n c e v s d r a i n to source voltage fi gu re 9 . un cl amp ed i nd uc tive s w i t c h i n g c a p a b i l i t y 0.001 0.01 0.1 1 10 100 1 50 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) -i as , avalanche current (a) 100 figure 10. 0 5 10 15 20 25 30 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 v gs = 0 v t j = 25 o c t j = 150 o c v gs , gate to source voltage (v) i g , gate leakage current (a) i gss vs v gss figure 11. 0.01 0.1 1 10 100 0.01 0.1 1 10 100 10 s 1 s dc 100 ms 10 ms 1 ms -i d , drain current (a) -v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c f o r w a r d b i a s s a f e operating area figure 12. 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 single pulse r t ja = 125 o c/w t a = 25 o c v gs = -10 v p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted www.datasheet.co.kr datasheet pdf - http://www..net/
FDMS6681Z p-channel powertrench ? mosfet www.fairchildsemi.com 5 ?2009 fairchild semiconductor corporation FDMS6681Z rev.c 4 figure 13. 0.001 0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transien t thermal response curve typical characteristics t j = 25 c unless otherwise noted www.datasheet.co.kr datasheet pdf - http://www..net/
FDMS6681Z p-channel powertrench ? mosfet www.fairchildsemi.com 6 ?2009 fairchild semiconductor corporation FDMS6681Z rev.c 4 dimensional outline and pad layout www.datasheet.co.kr datasheet pdf - http://www..net/
www.fairchildsemi.com 7 FDMS6681Z p-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation FDMS6681Z rev.c 4 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms auto-spm? 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